Accumulation of errors at hardware realization of algorithm of normalization

Abstract

Development of algorithms, designing of devices for their realization are the important factor of increase of productivity of computing systems. Earlier the algorithm of inversion of a divider and application of algorithm for performance of normalization of a vector by the author have been submitted. Then the description of devices of normalization of a vector has been given. At performance of machine arithmetic operations because of limitation of a digit grid inevitably there are error of a founding. Process of accumulation of errors of algorithm of normalization of a vector at his realization on devices of normalization in this clause with the help of methods of the numerical analysis is For restraint of growth of errors of calculations in these devices on adders for a mantissa to $m$ the basic bits is allocated in addition $q$ younger bits. As a result of researches attitudes between numbers $m$ and $q$, responding standard requirements of accuracy of the calculated result are established.